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From: elwell@osu-eddie.UUCP (Clayton M. Elwell)
Newsgroups: net.micro.68k
Subject: 68000 microcode cycle times
Message-ID: <364@osu-eddie.UUCP>
Date: Thu, 6-Jun-85 16:52:40 EDT
Article-I.D.: osu-eddi.364
Posted: Thu Jun  6 16:52:40 1985
Date-Received: Fri, 7-Jun-85 05:20:14 EDT
Distribution: net
Organization: Ohio State Univ., CIS Dept., Cols, Oh.
Lines: 9

I haven't bought the microcode listing & architecture description for the
68000 from the U.S. Patent Office, but from examination of the Motorola spec
sheet, and looking at when signals have to be ready, it looks as though it's
clocked by all CLK transitions, not just rising ones.  This makes some
sense;  it means you don't have to run 16MHz-32MHz signals around your board
(I've been bitten by that on a 80186--16MHz signals on a wire wrap are not
fun...).

--Clayton Elwell