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From: mash@mips.UUCP (John Mashey)
Newsgroups: net.micro.68k,net.arch
Subject: Re: RISC branch delay slots and booger-bears
Message-ID: <141@mips.UUCP>
Date: Thu, 6-Jun-85 12:37:57 EDT
Article-I.D.: mips.141
Posted: Thu Jun  6 12:37:57 1985
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Doug Pardee writes:
> 
> Some of the notes have indicated that these concerns are one and the
> same.  Sometimes, but not always.  Here's a choice counter-example:
> Some RISC machines have a "branch *after* next instruction" operation.
> This allows the pipeline to be used more efficiently.  It results in
> more efficient object code than conventional branch instructions, but
> it is a booger-bear to write an effective compiler for.

I'm not sure what a booger-bear is, but I guess it indicates difficulty.
This turns out not to be true. This function is usually called "filling the
branch delay slot", and it's normally done by a pipeline reorganizer
that's part of an assembler.  It's generally fairly easy to fill [90%+],
and it's not exceptionally difficult.  See  "VLSI Processor Architecture",
John Hennessy, IEEE Trans on Computers, Vol C-33, No 12, Dec 1984, or
"Reduced Instruction Set Computers", David A. Patterson, Comm ACM V28, 1
(Jan 1985), [for general discusion], or "Postpass code optimization of
pipeline constraints", J. L. Hennessy & T. R. Gross, ACM TOPLAS, v5, 3(Jul 83)
[for whole paper reorganizer].
-- 
-john mashey
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