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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.micro.68k,net.arch
Subject: Re: RISC
Message-ID: <5690@utzoo.UUCP>
Date: Mon, 17-Jun-85 15:08:19 EDT
Article-I.D.: utzoo.5690
Posted: Mon Jun 17 15:08:19 1985
Date-Received: Mon, 17-Jun-85 15:08:19 EDT
References: <639@vax2.fluke.UUCP> <2743@nsc.UUCP> <576@terak.UUCP>
Organization: U of Toronto Zoology
Lines: 18

> By the way, the Berkeley RISC-II chip has a 330 ns cpu cycle time.  The
> 10 MHz NS32016 can do a 32-bit register-to-register signed multiply in
> 8.3 usec.  The RISC-II cpu would have to be able to do the multiply in
> only 25 cpu cycles in order to compete.  All the cache in the world
> ain't gonna help...

The RISC II was designed by a bunch of grad students, using simplistic
design rules and mediocre MOS processing, with limited opportunity to try
again if the original chips didn't work.  The 10MHz NS32016 was done by
a swarm of professional silicon bashers, using professional facilities
and souped-up processes, over a long period of time with *many* design
iterations.  (In fact, too %@$@%#@% many for those of us who were waiting
for things to settle down and work...)  This comparison means little.

Also, multiplies are actually fairly infrequent operations in most programs.
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry