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From: gnu@sun.uucp (John Gilmore)
Newsgroups: net.micro.68k,net.micro.pc,net.arch
Subject: Re: x86/68x buses
Message-ID: <2306@sun.uucp>
Date: Sat, 15-Jun-85 05:13:57 EDT
Article-I.D.: sun.2306
Posted: Sat Jun 15 05:13:57 1985
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> From Ken Shoemaker, 386 Design Team, Intel, Santa Clara, Ca:
> If Mot had gone with pipelined address/data on the 68020R16,
> I'd guess that their memory access times (addr->data) would go from
> 115ns to 170ns.  However, they may use pipelining internally to access
> their cache, so they can never allow this extra margin for system 
> designers (does anyone know if this is true?).

I think the 68020 drives the address of prefetches (if there's not
already a cycle on the bus) but will not assert address strobe if it
hits the cache.  AS doesn't come out until the addresses are stable
anyway, so the cache lookup is overlapped with the address driver
propagation delay (and setup time on whoever's receiving the
addresses).  Serious MMUs start to translate the address before AS
anyway, so it actually helps to not have to latch the address, since
as fast as the CPU can drive it, the MMU can start looking it up, rather
than having it sit on the wrong side of a latch until a strobe comes out.

In a 180ns memory cycle it's VERY hard (both for CPU and for memory
subsystem) to run with Ken's proposed 170ns addr->data times.  It's
clear that the 68020 can access memory faster than dynamic ram can
respond.  There are plenty of solutions developed for mainframes (which
have had the same problem for a long time); the on-chip instruction
cache is one of them.  Ken's overlapping technique may be one that the
68020 design precludes.  Got any stats on how many 286 designs use the
technique, and how much time is really saved (e.g. is addr->data really
the bottleneck)?