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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.micro.68k,net.arch
Subject: Re: Re: RISC
Message-ID: <5722@utzoo.UUCP>
Date: Mon, 24-Jun-85 13:16:38 EDT
Article-I.D.: utzoo.5722
Posted: Mon Jun 24 13:16:38 1985
Date-Received: Mon, 24-Jun-85 13:16:38 EDT
References: <639@vax2.fluke.UUCP> <2743@nsc.UUCP> <576@terak.UUCP> <5691@utzoo.UUCP>, <4@intelca.UUCP>
Organization: U of Toronto Zoology
Lines: 13

> er, I don't think so...one of the basic concepts of RISCs as I understand
> them is to reduce the number of pipeline stages in the execution of
> instructions.  Adding another just to do an expansion/shuffleing of
> of opcode bytes flys directly in the face of that thinking.

Remember that the RISC is necessarily decoding its opcodes; not even on
a machine that simple is a numeric opcode a direct encoding of the internal
control signals.  The point is that the current instruction encoding was
chosen for simplicity, not compactness, and one can do better *without*
compromising the principles of the machine.
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry