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From: gnu@sun.uucp (John Gilmore)
Newsgroups: net.micro.68k,net.micro.pc,net.arch
Subject: Re: x86/68x buses ; two-level microcode
Message-ID: <2275@sun.uucp>
Date: Thu, 6-Jun-85 06:46:19 EDT
Article-I.D.: sun.2275
Posted: Thu Jun  6 06:46:19 1985
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> Ken Shoemaker says:                                   I still don't
> understand why since Mot gives you seperate address and data busses
> that they don't use them better, i.e., present early addresses to
> memory systems that could use them to an advantage.  This really
> does allow faster operation with slower memories at the cost of
> more pins on your package.  For what it's worth, it seems to me
> that Mot is wasting money providing seperate address/data pins
> with the utilization that they provide (unless they are not 
> pad limited on their die, and their yields are such that package
> costs are insignificant).  I mean, all those extra drivers do take
> up die space, and those extra pads could mean that the chip is not
> as small or as cheap as it could be....

Well, I was just reading a trade rag that quoted Intel and AMD as
having REDUCED the price of the 80186 by 50% to $15-20 for 25K.  We got
quotes of about $10 for 10MHz 68000's in quantity last month.
All those pins are really driving up the price...

One advantage of the 680x0 approach is that you don't have to surround
your CPU with glue to latch the addresses.  You can just wire address
pins straight to where they're going and they stay good for the entire
cycle.  I agree that there might be potential for speed improvement
here, so just think -- in a few years when the 68020 seems like a slow
machine, they'll have a few more tricks they can pull.

Here's some detail on memory cycle and address-to-data times for 68Ks:

	Part		ClkCyc	Clk/Mem	MemCyc	Addr->data
	68000L4	 	250ns	4      1000ns	630ns
	68000L10	100ns	4	400ns	230ns
	68010L10	100ns	4	400ns	235ns
	68000L12	 80ns	4	320ns	175ns
	68010L12	 80ns	4	320ns	175ns
	68020R12	 80ns	3	240ns	150ns
	68020R16	 60ns	3	180ns	115ns

Note that the 68000L4 was the first to be announced and the 68020R16
is the last to be announced.  There's a factor of 5 between the two
just in bus cycle times.  [I don't think you can buy 68000L4 anymore;
just about any die that runs at 4MHz also runs at 8 or more...]

>                                                       I believe
> Mot uses a two level microcode in the 68k and its followons...
> (can someone verify this?)  Does anyone have any idea what this
> means to its performance (with respect jumps and having to fill
> up the instruction queue).  Do they take two clocks to do a complete
> microcode lookup (the first to the first level, the second to the
> second level)?

The 68000, 68008, and 68010 have the same two-level ucode.  There is no
jump penalty though.  Basically they got tricky and noticed that if
they just made the microwords 197 bits wide that it would take up a lot
of chip area.  Instead, they figured out which bits really HAD to be
different for each microinstruction, and which bits might occur in
combinations that would occur more than once in the microcode.  It
turned out that they needed 544 different 17-bit microinstructions to
implement the 68000, but by sharing they only needed 336 180-bit nano
instructions.  There is no "pointer" from the microcode to the
nanocode; they are both addressed with the same address (the
micro-PC).  The trick is that the nanorom is decoded funny and a single
row can respond to multiple addresses.  These addresses have to be only
a few bits different from each other, so they had to be careful about
where each microinstruction went in the ROMs.  You can read all about
it in US Patent #4,325,121 by Tom Gunter and Harry "Nick" Tredennick.

I heard that most of the effort in making the 68010 was a large microcode
rewrite; the rest of the chip was reputedly similar to a 68000.  The
patent should be out by now but I haven't tracked it down.

I don't know what the microcode for 68020 looks like.

Got any similar tricks up your sleeve for the 386, Ken?