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From: phil@amdcad.UUCP (Phil Ngai)
Newsgroups: net.micro.68k,net.micro.pc,net.arch
Subject: Re: x86/68x buses ; two-level microcode
Message-ID: <1618@amdcad.UUCP>
Date: Wed, 12-Jun-85 01:17:54 EDT
Article-I.D.: amdcad.1618
Posted: Wed Jun 12 01:17:54 1985
Date-Received: Thu, 13-Jun-85 01:09:02 EDT
References: <344@osu-eddie.UUCP> <600@intelca.UUCP> <2275@sun.uucp>
Reply-To: phil@amdcad.UUCP (Phil Ngai)
Organization: AMD, Sunnyvale, California
Lines: 52
Xref: watmath net.micro.68k:899 net.micro.pc:4220 net.arch:1369

In article <2275@sun.uucp> gnu@sun.uucp (John Gilmore) writes:
>Well, I was just reading a trade rag that quoted Intel and AMD as
>having REDUCED the price of the 80186 by 50% to $15-20 for 25K.  We got
>quotes of about $10 for 10MHz 68000's in quantity last month.

Actually, we have reduced our price for the 80186 to below $15 in
quantity for devices in a plastic leaded chip carrier package. But
we haven't been making them very long; you can expect further price
reductions as we progress down the volume/price curve.

I speculate part of the reason the 68000 is so cheap is because there are
so many second sources, and thus, so much competition. Particularly from
Japanese vendors.

But a 64 pin package will alway be more expensive than a 40 pin package,
both for the vendor and for the user. Board space isn't free.

>One advantage of the 680x0 approach is that you don't have to surround
>your CPU with glue to latch the addresses.  You can just wire address
>pins straight to where they're going and they stay good for the entire
>cycle.

Only a very small system can do this. Any reasonable size system will have
to buffer the address lines anyway; address latches make great buffers.

>Here's some detail on memory cycle and address-to-data times for 68Ks:
>
>	Part		ClkCyc	Clk/Mem	MemCyc	Addr->data
>	68020R16	 60ns	3	180ns	115ns

These times are pretty incredible. I seriously doubt anyone will be able
to make a 0-wait state memory for the 68020R16 using cost-effective
memory devices such as 256K DRAMs. The addition of external memory
management hardware (which is required to use a 68K in a multi-tasking
environment) will, in addition to consuming more board space, make
a 0-wait state memory just about impossible. (for those who don't use
DRAMs every day, the average device has an access time of 150 nS. The
fastest I have seen run at 100 nS and cost a lot more. I suspect they
will never run much faster due to the timing requirements required to
set up a row address, operate the row address strobe, provide hold time,
set up a column address, operate the column address strobe, and provide
hold time for that.)

Of course, you can just put wait states in your memory and slow down the
system.
-- 
 A man could get elected President by promising to put
 the phone company back together.

 Phil Ngai (408) 749-5720
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