Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.2 9/18/84; site fortune.UUCP
Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxn!ihnp4!fortune!wall
From: wall@fortune.UUCP (Jim Wall)
Newsgroups: net.arch
Subject: Cache revisited
Message-ID: <5374@fortune.UUCP>
Date: Thu, 18-Jul-85 12:19:52 EDT
Article-I.D.: fortune.5374
Posted: Thu Jul 18 12:19:52 1985
Date-Received: Sat, 20-Jul-85 07:32:21 EDT
Distribution: net
Organization: Fortune Systems, Redwood City, CA
Lines: 30


    I have a feeling that this topic may once again start the
religious wars of cache types and implimentations, but just maybe 
I can get the info that I'm looking for.  Given a multiuser 
UNIX environment, and given a cache that is split so that user
and supervisor/kernal are separate; what kind of performance 
improvment will the cache yield. More information: The cache is
a simple direct mapped implimentation, as the CPU fetches something
from RAM (I/O is not cached obviously), it is stored in the cache.
If that physical address is ever used again, the data will come from
the cache. 

    So where this will aid in is program loops, and often used 
routines. The cache is 16K bytes split into 8K for user and 8K for
supervisor. THE QUESTION IS:  in UNIX how much improvement can the 
cache make? Let's face it, you won't be making a 70% - 90% hit rate.

   O.K., an extra credit part to the problem: If the CPU were a 
68020 with the internal 256 byte direct mapped instruction cache, is 
there a need for the external cache?

   						-Jim Wall
						...amd!fortune!wall

P.S. Both Altos and Charles River Data had both the 020 cache and
an external 8K cache, Dual did not. Anyone know why? Not that I'm 
trying to have someone else do my design work, I believe that for the
external cache to be really useful, the system architecture must be
designed for the cache, such as 64 bit wide memory, or block transfers
on cache misses. Does CRD or Altos do any of these?