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From: louie@umd5.UUCP
Newsgroups: net.arch
Subject: Re: Re: Re: RISC (really on multiplication d
Message-ID: <679@umd5.UUCP>
Date: Tue, 23-Jul-85 11:13:45 EDT
Article-I.D.: umd5.679
Posted: Tue Jul 23 11:13:45 1985
Date-Received: Thu, 25-Jul-85 06:33:18 EDT
References: <149@mips.UUCP> <600005@pbear.UUCP> <493@mmintl.UUCP> <233@weitek.UUCP> <1202@sjuvax.UUCP>
Reply-To: louie@umd5.UUCP (Louis Mamakos)
Organization: U of Md, CSC, College Park, Md
Lines: 32

In article <1202@sjuvax.UUCP> jss@sjuvax.UUCP (J. Shapiro) writes:
>> > ... one multiplies two words and wants a word result.
>> > But hardware multiplies invariably generate a two word result, leaving the
>> > high-order word to be allowed for and/or disposed of.
>> The Decsystem-10 & 20 has an instruction IMUL which does exactly what you
>> want. It Multiplies a 36bit value by another 36 bit value and gives a 36
>> bit result. They also have a divide which divides a 36 bit number.
>
>For comparison and elucidation, so do:
>
>	VAX
>	PDP-11
>	National 32016 and family
>	Motorola 68000, 68020, 6800, 6809, ...
>	Zilog Z8000
>	Z80

Huh?  You think that a Z80 is clever enough to MULTIPLY?  Mine sure doesn't.
By the way, the Sperry 1100 series also had a Multiple Single Integer (MSI)
instruction that give a 36 bit result from two 36 bit operands.  This seems
to get used much more often (at least in my code) than the Multipy Integer(MI)
instruction that give a 72 bit result.

>	Intel 8086, 80186, 82086
>
>Jon Shapiro


-- 
Louis A. Mamakos WA3YMH   University of Maryland, Computer Science Center
 Internet: louie@umd5.arpa
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