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Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxn!ihnp4!mgnetp!ltuxa!ttrdc!levy
From: levy@ttrdc.UUCP (Daniel R. Levy)
Newsgroups: net.arch
Subject: Re**n: RISC (really on multiplication d
Message-ID: <298@ttrdc.UUCP>
Date: Wed, 24-Jul-85 19:26:12 EDT
Article-I.D.: ttrdc.298
Posted: Wed Jul 24 19:26:12 1985
Date-Received: Fri, 26-Jul-85 06:43:39 EDT
References: <149@mips.UUCP> <600005@pbear.UUCP> <493@mmintl.UUCP> <233@weitek.UUCP> <1202@sjuvax.UUCP>
Organization: AT&T, Computer Systems Division, Skokie, IL
Lines: 30

ss@sjuvax.UUCP (J. Shapiro)  <1202@sjuvax.UUCP> quotes and tells us:

>> > But hardware multiplies invariably generate a two word result, leaving the
>> > high-order word to be allowed for and/or disposed of.
>> 
>> The Decsystem-10 & 20 has an instruction IMUL which does exactly what you
>> want. It Multiplies a 36bit value by another 36 bit value and gives a 36
>> bit result. They also have a divide which divides a 36 bit number.
>
>For comparison and elucidation, so do:
>
>	VAX
>	PDP-11
>	National 32016 and family
>	Motorola 68000, 68020, 6800, 6809, ...
                               ^^^^
>	Zilog Z8000
>	Z80
>	Intel 8086, 80186, 82086

Since when did Motorola add such fancy hardware to their lowly 6800?

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