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From: steve@kontron.UUCP (Steve McIntosh)
Newsgroups: net.arch
Subject: RISC and MIPS
Message-ID: <419@kontron.UUCP>
Date: Fri, 26-Jul-85 12:31:02 EDT
Article-I.D.: kontron.419
Posted: Fri Jul 26 12:31:02 1985
Date-Received: Sun, 28-Jul-85 07:24:37 EDT
Distribution: net
Organization: Kontron Electronics, Irvine, CA
Lines: 104

[ From the DTACK newsletter #44 (August 1985) ]

"RISC ARCHITECTURES:

Although simplified instruction sets were pioneered by Seymor Cray  and
by IBM's 801 project, the RISC concept was popularized by Patterson of
UC Berkeley, assisted by the traditional slave labor available to a
university professor. UC Berkley provides a very nice ivory tower where
competitive pressures and real-world pragmatism need not be considered.

Patterson provided a number of benchmarks which conclusively proved
that the RISC was superior to anything around. He also chose the
benchmarks, controlled the conditions of the tests, and most
particularly, chose to perform benchmarks in the HLL language 'C'
exclusively. This provides opportunities for much mischief (as when
Intel benchmarks its 16-megabyte addressing-range 286 EXCLUSIVELY in a
64k baby-pen).

( Author  goes on  for 7  paragraphs ...   general  description of RISC,
attributes  performance  advantages  of  RISC  architecture  (if any) to
sizable overlapping register set ...  lack of software support for new 
chips etc...) 

WHAT IS A MIP?

Technically, a MIP is a million instructions per second. OK then,
what's an instruction? Ah! That's a very good question!

Take, for example, the following 68000 instruction:

	MOVE.W D7,(A3)+

That instruction stores the lower word of the 32-bit register D7 at the
address contained in the 32-bit address register A3, and then
increments A3 by two (two bytes = one word). Here is that instruction's
equivalent for the Nat Semi 32016:

	MOVW D7,(SB)
	ADDQD 2,SB

The same operation in a hypothetical RISC machine:

	MOVE R7,(R#)
	LOAD 2,R4
	ADD  R4,R#

For simplicity, suppose that those three computers each performed that
equivalent instruction (or instruction sequence) in exactly one
microsecond. Then the 68000 would be operating at 1 MIP, the 32000
series at 2 MIPS, and the hypothetical RISC machine at 3 MIPS. 

EACH COMPUTER WOULD BE PERFORMING EXACTLY THE SAME AMOUNT OF WORK!

When a RISC advocate proudly points to the MIP performance rating of
his preferred architecture, remember that a RISC HAS to run at a lot
more MIPS than a CISC machine just to keep up. WHAT IS A MIP, INDEED!

THE VON NEUMANN BOTTLENECK:

No von Neumann machine can run faster than allowed by its
bus-bandwidth. Both RISC and CISC architectures are von Neumann
machines. Let us examine those three equivalent instruction (sequences)
from a bus-bandwidth standpoint:

The 68000 requires two memory cycles, the 32016 three memory cycles
and the RISC machine either three or four memory cycles depending on
whether it includes a LOAD QUICK instruction which contains small
integers inside the instruction field.

In fact, the 68000 executes that instruction (singular in the case of
the 68000) in exactly two memory cycles (eight clocks). The 32016
requires AT LEAST three memory cycles (12 clocks) to execute, and can
be even slower than that if the instructions are not word aligned.
(68000 instructions are ALWAYS word aligned) The hypothetical risk
machine requires 3 or 4 memory cycles to perform the same operation.

Therefore, the poor little 68000, operating at a mere 1 MIPS, is
running AT LEAST 50% faster than a 2 MIPS 32016 and 50% to 100% faster
than a 3 MIPS RISC machine!

To further emphasize this important point, our hypothetical RISC
machine would have to have a memory cycle time 50% to 100% faster than
the 68000 to have equal performance, and that would give it a 4.5 (50%
faster) or 6.0 (100% faster) MIPS rating. If the 68000 is running at
12.5Mhz with zero wait states using 120 nsec DRAM (say, two megabytes
of it) then JUST WHERE DO WE FIND DRAM FOR THAT RISC WHICH IS 50% TO
100% FASTER? (At an affordable price - srmc)

... Since a 68000 in fact performs that instruction in 640 nsec,
corresponding to 1.56 MIPS, that hypothetical RISC machine would have
to run at 7.03 to 9.38 MIPS to equal the MIPS 68000! WE STRONGLY
SUGGEST THAT YOU IGNORE THE MIPS RATING OF RISC MACHINES! RISC machines
HAVE to have a high MIPS rating just to get out of their own way!"

- DTACK GROUNDED		$15/10 issues (US & Canada)
  1415 E. McFadden, Ste.E	$25/10 issues elsewhere
  Santa Ana CA 92705	        (US funds)

=======================================================================
I do not work for DTACK, I just enjoy the newsletter. Flames to them,
please (they like it, and DO publish flame letters that they get in
response to the newsletter.)
=======================================================================
Steve McIntosh, Kontron Electronics, Irvine CA / usual disclaimers /