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From: srm@nsc.UUCP (Richard Mateosian)
Newsgroups: net.arch
Subject: Multiplication
Message-ID: <3043@nsc.UUCP>
Date: Sun, 28-Jul-85 13:01:12 EDT
Article-I.D.: nsc.3043
Posted: Sun Jul 28 13:01:12 1985
Date-Received: Tue, 30-Jul-85 06:37:45 EDT
References: <149@mips.UUCP> <600005@pbear.UUCP> <493@mmintl.UUCP> <233@weitek.UUCP> <1202@sjuvax.UUCP> <5825@utzoo.UUCP>
Reply-To: srm@nsc.UUCP (Richard Mateosian)
Organization: National Semiconductor, Sunnyvale
Lines: 13

In article <5825@utzoo.UUCP> henry@utzoo.UUCP (Henry Spencer) writes:

>My (admittedly dim) memory
>of the Z8000 is that its multiply instructions yield double-width results.

Since I have a copy of "Programming the Z8000" by Richard Mateosian close at
hand, I can tell you that the Z8000 has 16x16 -> 32  and  32x32 -> 64 bit
multiplies and the corresponding divides.  I believe that the Z80000 will
have all the combinations you might want.  (Perhaps I should say "has"
rather than "will have", since I saw a Z80000 wafer at NCC.)
-- 
Richard Mateosian
{cbosgd,fortune,hplabs,ihnp4,seismo}!nsc!srm    nsc!srm@decwrl.ARPA