Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.3 alpha 4/15/85; site weitek.UUCP Path: utzoo!linus!philabs!cmcl2!seismo!harvard!think!mit-eddie!genrad!decvax!decwrl!spar!turtlevax!weitek!mahar From: mahar@weitek.UUCP (mahar) Newsgroups: net.arch Subject: Re: RISC and MIPS Message-ID: <237@weitek.UUCP> Date: Mon, 29-Jul-85 13:33:57 EDT Article-I.D.: weitek.237 Posted: Mon Jul 29 13:33:57 1985 Date-Received: Thu, 1-Aug-85 00:14:56 EDT References: <419@kontron.UUCP> Distribution: net Organization: Weitek Corp. Sunnyvale Ca. Lines: 87 Summary: fun with numbers In article <419@kontron.UUCP>, steve@kontron.UUCP (Steve McIntosh) writes: > "RISC ARCHITECTURES: > what's an instruction? Ah! That's a very good question! > Take, for example, the following 68000 instruction: > > MOVE.W D7,(A3)+ > > That instruction stores the lower word of the 32-bit register D7 at the > address contained in the 32-bit address register A3, and then > increments A3 by two (two bytes = one word). > The same operation in a hypothetical RISC machine: > > MOVE R7,(R#) > LOAD 2,R4 > ADD R4,R# On the Berkeley RISC, the equivalent istruction sequence is: MOVE R7,(R4) ADD #2,R4,R4 > > For simplicity, suppose that those three computers each performed that > equivalent instruction (or instruction sequence) in exactly one > microsecond. Then the 68000 would be operating at 1 MIP, the 32000 > series at 2 MIPS, and the hypothetical RISC machine at 3 MIPS. > > EACH COMPUTER WOULD BE PERFORMING EXACTLY THE SAME AMOUNT OF WORK! > > When a RISC advocate proudly points to the MIP performance rating of > his preferred architecture, remember that a RISC HAS to run at a lot > more MIPS than a CISC machine just to keep up. WHAT IS A MIP, INDEED! I agree that MIP is not a very good measure of computer performance. A rule of thumb that I have heard is that the VAX 780 is 1 MIP. If your computer does more work in less time then a 780 it is faster then 1 MIP. If it does less, it's slower. > > THE VON NEUMANN BOTTLENECK: > > No von Neumann machine can run faster than allowed by its > bus-bandwidth. Both RISC and CISC architectures are von Neumann > machines. Let us examine those three equivalent instruction (sequences) > from a bus-bandwidth standpoint: > > The 68000 requires two memory cycles, the 32016 three memory cycles > and the RISC machine either three or four memory cycles depending on > whether it includes a LOAD QUICK instruction which contains small > integers inside the instruction field. Once again the Berkeley RISC is two memory cycles. > > In fact, the 68000 executes that instruction (singular in the case of > the 68000) in exactly two memory cycles (eight clocks). The 32016 > requires AT LEAST three memory cycles (12 clocks) to execute, and can > be even slower than that if the instructions are not word aligned. > (68000 instructions are ALWAYS word aligned) The hypothetical risk > machine requires 3 or 4 memory cycles to perform the same operation. Since the Berkely machine is also two memory cycles (2 clocks), this is a tie. > > Therefore, the poor little 68000, operating at a mere 1 MIPS, is > running AT LEAST 50% faster than a 2 MIPS 32016 and 50% to 100% faster > than a 3 MIPS RISC machine! > > To further emphasize this important point, our hypothetical RISC > machine would have to have a memory cycle time 50% to 100% faster than > the 68000 to have equal performance, and that would give it a 4.5 (50% > faster) or 6.0 (100% faster) MIPS rating. If the 68000 is running at > 12.5Mhz with zero wait states using 120 nsec DRAM (say, two megabytes > of it) then JUST WHERE DO WE FIND DRAM FOR THAT RISC WHICH IS 50% TO > 100% FASTER? (At an affordable price - srmc) With that same 120 nsec DRAM, the Berkely RISC could run at 8 Mhz. Since the 68000 does it work in 8 cycles it takes 8/12.5 or about 640 nsec. The Berkely RISC does its work in 2 cycles. So, at 8 Mhz it takes 2/8 or 250 nsec. All for the same memory band width. In fact, however, the Berkeley RISC only runs at about 4 Mhz. The memory bandwidth is 250 nsec. The same sequence would be 500 nsec. A 4 Mhz RISC takes 25/32 the time to do what a 12.5 Mhz 68000 would do. I agree, In the example given the RISC took twice as many instructions to do the same job. The MIP designation is ambiguous. One must look at how much work is done in a given amount of time.