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From: wfmans@ihuxb.UUCP (w. mansfield)
Newsgroups: net.arch
Subject: Re: RISC and MIPS
Message-ID: <1124@ihuxb.UUCP>
Date: Thu, 1-Aug-85 14:43:18 EDT
Article-I.D.: ihuxb.1124
Posted: Thu Aug  1 14:43:18 1985
Date-Received: Sat, 3-Aug-85 02:09:33 EDT
References: <419@kontron.UUCP>
Distribution: net
Organization: AT&T Bell Laboratories
Lines: 27

No, I'n not going to repeat the whole article.
It contrasted RISC and CISC micros and determined from the MIP
ratings that RISC micros are silly.

1.  MIP rating have been discussed here before, and all agree that
    they are a stupid measure of anything.  A RISC will generally
    achieve one instruction per cycle (that's the goal, anyway),
    while a CISC requires many cycles to do an instruction.  Also,
    typical CISCs report their MIP ratings for their shortest
    instruction (NOP?), and inflate their MIPs accordingly.
    
2.  The basic premise of RISC machines is to do the instructions
    that are used often very fast.  Indexing is a complex operation
    that just isn't done that often (and which can usually be
    simplified by good compilers (e.g. sophisticated compilers as
    used by 801 and MIPS projects)).
    
3.  It is becoming apparent to folks doing objective measurements
    from models of RISCs that much of the performance of the RISC
    isn't from the reduced instructions, its from the register
    windows et.al.  Agreed, these architectural improvements aren't
    part of RISC per se, but try getting them to fit in silicon
    along with a complex instruction set.
    
    No flames, just observations.  Newsletter sounds interesting,
    like a reprint of net.bellicose.