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From: armstron@sjuvax.UUCP (L. Armstrong)
Newsgroups: net.arch
Subject: Re: Re: RISC and MIP
Message-ID: <1231@sjuvax.UUCP>
Date: Fri, 2-Aug-85 08:20:47 EDT
Article-I.D.: sjuvax.1231
Posted: Fri Aug  2 08:20:47 1985
Date-Received: Sun, 4-Aug-85 09:08:35 EDT
References: <419@kontron.UUCP> <237@weitek.UUCP> <2192@amdcad.UUCP>
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Organization: St. Joseph's University, Phila. PA.
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> Just what is a MIP, anyway? Million Instructions Per?
> Perhaps you mean MIPS, as in "the VAX 780 is rated at 1 MIPS".

I just kinda' jumped into this discussion, but I have a feeling I know what
you're talking about anyway.  A "MIPS" can (and in fact does) refer to something
more than Million Instructions Per Second", but also to a type of architecture
philosphy called "Microprocessor without Interlocked Pipe(line) Stages."  It
is originally a Stanford project, initiated by Thomas Gross, and in a nutshell
the philosphy attempts to avoid ever having to "flush" out a pipeline if (for
example) a certain brach is taken, and the things currently existing in the
pipeline are no longer applicable.

-- 

NAME		Len Armstrong
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