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From: george@mnetor.UUCP (George Hart)
Newsgroups: net.graphics
Subject: Re: Orphaned Response
Message-ID: <1660@mnetor.UUCP>
Date: Thu, 1-Aug-85 10:08:45 EDT
Article-I.D.: mnetor.1660
Posted: Thu Aug  1 10:08:45 1985
Date-Received: Thu, 1-Aug-85 11:26:41 EDT
References: <10570@rochester.UUCP> <6700022@datacube.UUCP>
Reply-To: george@mnetor.UUCP (George Hart)
Organization: Computer X (CANADA) Ltd., Toronto, Ontario, Canada
Lines: 31
Summary: 

In article <6700022@datacube.UUCP> shep@datacube.UUCP writes:
>
>I am not familiar with the two architectures (CMU WARP,BBN Butterfly) mentioned

FYI:

There is an excellent discussion on multiprocessing technology in the
June/85 issue of IEEE Computer where the WARP and Butterfly architectures
are discussed (brief excerpts below).

The Warp is (or will be, the article speaks of it in the future tense)
a systolic array machine, consisting of 10 processing elements, each
10MFLOPS, interconnected via custom VLSI. GE and Honeywell are
industrial partners in this with CMU.  There exists a 9 element, 10
MIPS prototype.

The Butterfly is a switch based machine using 8Mhz M68k as processing
elements, AMD-2901 bit slicers as MMU's, and custom VLSI for
switchers.  A 128 node machine has been delivered and is supposed to be
available on Arpanet (to/by whom, I don't know).  If fully populated
with memory, that 128 node machine will have 512 Mb of *global*(!!)
memory since each node's local memory can be globally accessed via the
butterfly switch.
-- 


Regards,

George Hart, Computer X Canada Ltd.
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