Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84 SMI; site sun.uucp Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxn!ihnp4!qantel!intelca!amdcad!decwrl!sun!guy From: guy@sun.uucp (Guy Harris) Newsgroups: net.micro.68k,net.micro.16k Subject: Re: PDP11s vs the micros Message-ID: <2547@sun.uucp> Date: Fri, 2-Aug-85 03:31:56 EDT Article-I.D.: sun.2547 Posted: Fri Aug 2 03:31:56 1985 Date-Received: Sat, 3-Aug-85 10:31:14 EDT References: <1617@hao.UUCP> <847@mako.UUCP> <2422@sun.uucp> <2994@nsc.UUCP> <2506@sun.uucp> <877@mako.UUCP> Organization: Sun Microsystems, Inc. Lines: 79 Xref: watmath net.micro.68k:1034 net.micro.16k:359 > >Yes, you can use it as a stack machine (make both operands use the TOS > >addresing mode)... How many 32xxx instructions use TOS for both operands, > >and how many use a register, or register relative/memory space, or...? > > Any instruction that uses "general" addressing could care less if the > operands are "TOS..., register, or register relative/memory space, or..." Yes, I already knew that. *That was my entire point.* Since a large list of instructions use "general" addressing for both their operands, and since that means they can all use all the aforementioned addressing modes, I submit that the NS32xxx isn't a "p-machine". If it *is* a "p-machine", so is the CCI Power 6/32; it has auto-increment SP and auto-decrement SP addressing modes, and you could easily has the assembler to accept a TOS addressing mode and generate (sp)+, -(sp), or (sp) addressing modes for it. Somehow, I don't think removing all auto-incrementing or auto-decrementing addressing modes from a machine's instruction set makes it a "p-machine", though. > It is easier to count the instructions that do not use TOS for one operand. > A quick perusal shows . All the "mainstream" > operations can have any general addressing mode for either operand. My point exactly. When I said "how many 32xxx instructions use...", I didn't mean "how many instructions as listed in the 'Instruction Set Reference Manual' use...", I meant "how many instructions as written by assembly-language programmers and as generated by compilers use..." I don't have the "Instruction Set Reference Manual"; will "NS16032S-6, NS16032-4 High Performance Microprocessors (Preliminary - November 1982)" do? > ...and the SP behaves in a reasonable way, depending on the access > class: > > addd tos,tos first operand is popped (SP incremented), > rd rmw second is only modified (SP unchanged) > > jump tos tos -> PC (SP unchanged) > addr > > negd tos,tos first operand is popped (SP incremented), > rd wr second operand is pushed (SP decremented) > > acbd -1,tos,label operand is decremented, loop until operand > q rmw disp reaches zero. (SP unchanged) As I pointed out, a VAX or Power 6 assembler could do that too. (The PDP-11 and M68000 don't have enough two-operand instructions with both operands specified by general addressing modes to make this worthwhile.) Turn "tos" into (sp) for most one-operand instructions, turn the first "tos" into (sp)+ and the second into (sp) for two-operand instructions that fetch both operands, and the first into (sp)+ and the second into -(sp) for two-operand instructions that fetch only the first operand. (Punt the 3-operand instructions.) > As to Nati TOS usefulness to the mythical "p-machine", I'm working on a Z80 > emulator that uses the 32032 SP as the Z80 PC. Another thing we're > exploring is using the SP as a Smalltalk virtual stack pointer. What does this have to do with "Nati TOS usefulness to the mythical 'p-machine'"? I have no idea what the person had in mind when he called the 32xxx a "p-machine". The logical assumption is that he meant "p-code engine"; P-code engines are generally stack machines which the NS32xxx is *not*, any more than the VAX is. You can treat it as a stack machine, but you don't *have* to (and probably don't want to; it'll run faster as a general-register machine). If you are merely referring to architectural features that make certain bits of coding work nicely, then the PDP-11 is a "p-machine" in that sense - note the use of "jmp @(r4)+" for threaded code. I presume the TOS addressing mode is useful for the Z80 simulator because it's the only addressing mode that does any sort of auto-incrementing of a register - i.e., instruction fetch is done with "movw tos, ". You can do the same on machines like the PDP-11, VAX, and M68000 by doing move (reg)+, where "reg" is a register chosen for use as the simulator's PC. Guy Harris