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From: GJC@MIT-MC.ARPA (George J. Carrette)
Newsgroups: fa.info-vax
Subject: 8600
Message-ID: <[MIT-MC.ARPA].639339.850909.GJC>
Date: Mon, 9-Sep-85 23:09:18 EDT
Article-I.D.: <[MIT-MC.ARPA].639339.850909.GJC>
Posted: Mon Sep  9 23:09:18 1985
Date-Received: Wed, 11-Sep-85 05:37:57 EDT
Sender: daemon@ucbvax.ARPA
Reply-To: info-vax@ucb-vax.arpa
Organization: The ARPA Internet
Lines: 5

are people aware of any differences in how access violation
conditions are handled and signalled on the 8600 vs other
processor types? (under vms). are there any instructions that
use more registers or use stack space where before they did
not use stack space?