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From: ed@mtxinu.UUCP (Ed Gould)
Newsgroups: net.arch
Subject: Re: Re: Cache Revisited
Message-ID: <455@mtxinu.UUCP>
Date: Fri, 30-Aug-85 19:27:24 EDT
Article-I.D.: mtxinu.455
Posted: Fri Aug 30 19:27:24 1985
Date-Received: Sat, 7-Sep-85 04:11:35 EDT
References: <170@mips.UUCP>
Reply-To: ed@mtxinu.UUCP (Ed Gould)
Distribution: net
Organization: mt Xinu, Berkeley, CA
Lines: 19

In article <170@mips.UUCP> mash@mips.UUCP (John Mashey) writes:

>                                                 Consider the ultimate
>case: a smart compiler and a machine with many registers, such that
>most code sequences fetch a variable just once, so that most data references
>are cache misses.  Passing arguments in registers also drives the hit
>rate down.

With this ultimate machine/compiler combination it seems intuitively
that a data cache would then be a *bad* idea, since having a cache
can't be faster than an uncached memory reference (for what would
be a miss) and is often slower.  We can then use the real estate saved
for even more registers!

-- 
Ed Gould                    mt Xinu, 2910 Seventh St., Berkeley, CA  94710  USA
{ucbvax,decvax}!mtxinu!ed   +1 415 644 0146

"A man of quality is not threatened by a woman of equality."