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From: bobbyo@celerity.UUCP (Bob Ollerton)
Newsgroups: net.arch
Subject: Re: RISC and MIPS
Message-ID: <342@celerity.UUCP>
Date: Tue, 3-Sep-85 13:22:34 EDT
Article-I.D.: celerity.342
Posted: Tue Sep  3 13:22:34 1985
Date-Received: Sun, 8-Sep-85 16:18:52 EDT
References: <419@kontron.UUCP> <2300001@uicsl> <1093@ames.UUCP> <29898@lanl.ARPA>
Reply-To: bobbyo@celerity.UUCP (Bob Ollerton)
Organization: Celerity Computing, San Diego, Ca.
Lines: 36
Summary: 


I agree that using some real, heavy duty, commercial codes can be
a good way of measuring the performance of CPU architectures.
RISC CPUs can sometimes be difficult to get a handle on if the
particular implementation is strong in some cases, and weak in others.

Here are some results from a Finite Element Modeler from Swanson Analysis,
called ANSYS.  It is a large fortran program written quite a few years
ago and continuously enhanced.  It uses both single and double precision
math, I/O, and lots of virtual memory.

Please note that these results while supplied by the various vendors,
are being presented to you from a biased source; Me.

---------------------------------------------------------------------


Combined ANSYS benchmarks SP1, SP2, SP3, SP4:

Vendor           CPU seconds
-----------------------------

Prime 750          6505 
RIDGE 32           5750
APOLLO X60         5372
VAX 780 w/fpa      4574
DG MV8000          3290
IBM 4341-1         2973
Celerity C1200     2506


-- 
Bob Ollerton; Celerity Computing; 
9692 Via Excelencia; San Diego, Ca 92126; (619) 271 9940
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