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From: davet@oakhill.UUCP (Dave Trissel)
Newsgroups: net.arch
Subject: Re: Re: Cache revisited
Message-ID: <518@oakhill.UUCP>
Date: Fri, 6-Sep-85 00:49:40 EDT
Article-I.D.: oakhill.518
Posted: Fri Sep  6 00:49:40 1985
Date-Received: Tue, 10-Sep-85 08:30:50 EDT
References: <5374@fortune.UUCP> <901@loral.UUCP> <2583@sun.uucp> <5459@fortune.UUCP> <484@oakhill.UUCP> <48@intelca.UUCP>
Reply-To: davet@oakhill.UUCP (Dave Trissel)
Distribution: net
Organization: Motorola Inc. Austin, Tx
Lines: 15

In article <48@intelca.UUCP> kds@intelca.UUCP (Ken Shoemaker) writes:

>> BTW, the 10 to 15 percent cache hit rate is nothing to sneeze at when you look
>> at real performance gain.  Take a hit rate of 10 percent.  That 10 percent
>
>This assumes, of course, that there is no miss penalty...

There is no penalty since the instruction address is sent both to the cache
and the bus control unit at the same time.  A hit causes the bus controller
to avoid the bus cycle, and as I understand it, without any loss of external
bus effeciency if another operation is queued.

  --  Dave Trissel
      Motorola Semiconductor Inc.  {ihnp4,seismo}!ut-sally!oakhill!davet
      Austin, Texas