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Posting-Version: version B 2.10.1 6/24/83; site mmintl.UUCP
Path: utzoo!linus!philabs!pwa-b!mmintl!franka
From: franka@mmintl.UUCP (Frank Adams)
Newsgroups: net.arch
Subject: Re: Re: Cache Revisited
Message-ID: <645@mmintl.UUCP>
Date: Mon, 9-Sep-85 22:59:32 EDT
Article-I.D.: mmintl.645
Posted: Mon Sep  9 22:59:32 1985
Date-Received: Thu, 12-Sep-85 21:47:50 EDT
References: <170@mips.UUCP> <455@mtxinu.UUCP>
Reply-To: franka@mmintl.UUCP (Frank Adams)
Distribution: net
Organization: Multimate International, E. Hartford, CT
Lines: 17
Summary: remember context switching


In article <455@mtxinu.UUCP> ed@mtxinu.UUCP (Ed Gould) writes:
>In article <170@mips.UUCP> mash@mips.UUCP (John Mashey) writes:
>
>>                                                 Consider the ultimate
>>case: a smart compiler and a machine with many registers, such that
>>most code sequences fetch a variable just once, so that most data references
>>are cache misses.  Passing arguments in registers also drives the hit
>>rate down.
>
>With this ultimate machine/compiler combination it seems intuitively
>that a data cache would then be a *bad* idea, since having a cache
>can't be faster than an uncached memory reference (for what would
>be a miss) and is often slower.  We can then use the real estate saved
>for even more registers!

Not necessarily.  When a context switch takes place, you would have to
save all the registers.  The cache can, at worst (best?) be dumped.