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From: lotto@talcott.UUCP (Jerry Lotto)
Newsgroups: net.micro,net.micro.pc,net.arch
Subject: Memory timing and other picture postcards
Message-ID: <503@talcott.UUCP>
Date: Sun, 8-Sep-85 10:09:49 EDT
Article-I.D.: talcott.503
Posted: Sun Sep  8 10:09:49 1985
Date-Received: Wed, 11-Sep-85 06:08:40 EDT
Organization: Harvard Univ. Chem. Dept.
Lines: 34
Keywords: memory access time crystal wait state
Xref: watmath net.micro:11916 net.micro.pc:5261 net.arch:1766

[ISIB - this has been sent directly, do not digest]

	I am interested in calculating various parameters
for a "fast" AT system but my "hardware education" is
nominal at best.  So, would the hardware types out there
please take a stab at the following questions?  I am knee
deep in 286 manuals and not much closer to the answers.

1) How do you calculate the maximum allowable access time
for a RAM (comparing the AT at 6 vs 10 MHz for example)
without wait states?

2) The inverse of 1 (How many wait states for a given speed
and memory?) for the type of memory subsystem in an AT.

3) What other chips in the AT are speed sensitive in the
6-10 MHz range?

4) What kinds of problems are unique to faster systems (xs
heat etc.) and what practical solutions are available?

5) What references are useful to obtain enough of an
understanding of system design to answer these questions
myself?

	Thanks in advance for all replies.  I will summarize
and report answers to 1-5 above if they are not posted.
-- 

Gerald Lotto - Harvard Chemistry Dept.

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