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From: patc@tekcrl.UUCP (Pat Caudill)
Newsgroups: net.arch
Subject: Re: Re: Cache Revisited
Message-ID: <254@tekcrl.UUCP>
Date: Mon, 16-Sep-85 09:23:36 EDT
Article-I.D.: tekcrl.254
Posted: Mon Sep 16 09:23:36 1985
Date-Received: Wed, 18-Sep-85 05:09:50 EDT
References: <170@mips.UUCP> <455@mtxinu.UUCP> <645@mmintl.UUCP>
Reply-To: patc@tekcrl.UUCP (Pat Caudill)
Distribution: net
Organization: Tektronix, Beaverton OR
Lines: 15

>In article <170@mips.UUCP> mash@mips.UUCP (John Mashey) writes:
>
>>                                                 Consider the ultimate
>>case: a smart compiler and a machine with many registers, such that
>>most code sequences fetch a variable just once, so that most data references
>>are cache misses.  Passing arguments in registers also drives the hit
>>rate down.

	If you have read the article on the IBM 801 project this was just
what they did. The cache was the register set (which was medium large -
32 registers). But there was a very very smart compiler which optimized
register usage even across subroutine calls. Go look at the article it
was published in a SIGPLAN several years ago. (It was by the compiler
writer)
			Pat Caudill


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