Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site mips.UUCP Path: utzoo!linus!decvax!decwrl!Glacier!mips!mash From: mash@mips.UUCP (John Mashey) Newsgroups: net.arch Subject: Re: Re: Cache Revisited Message-ID: <193@mips.UUCP> Date: Thu, 19-Sep-85 21:30:49 EDT Article-I.D.: mips.193 Posted: Thu Sep 19 21:30:49 1985 Date-Received: Sat, 21-Sep-85 11:48:37 EDT References: <170@mips.UUCP> <455@mtxinu.UUCP> <645@mmintl.UUCP> <254@tekcrl.UUCP> Distribution: net Organization: MIPS Computer Systems, Mountain View, CA Lines: 17 Pat Caudill writes: > If you have read the article on the IBM 801 project this was just > what they did. The cache was the register set (which was medium large - > 32 registers). But there was a very very smart compiler which optimized > register usage even across subroutine calls. Go look at the article it > was published in a SIGPLAN several years ago. The referenced reference is: M. Auslander, M. Hopkins, "An Overview of the PL.8 Compiler", Proc. SIGPLAN Symp. Compiler Construction, ACM, Boston, June 1982, 22-31. A useful related article is: F. Chow, J. L. Hennessy, "Register Allocation by Priority-Based Coloring", Proc. SIGPLAN Symp. Compiler Construction, ACM, Montreal, June 1984, 222-232. -- -john mashey UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash DDD: 415-960-1200 USPS: MIPS Computer Systems, 1330 Charleston Rd, Mtn View, CA 94043 Brought to you by Super Global Mega Corp .com