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From: jvz@loral.UUCP (John Van Zandt)
Newsgroups: net.arch
Subject: Re: Tagged architectures
Message-ID: <926@loral.UUCP>
Date: Mon, 23-Sep-85 00:13:01 EDT
Article-I.D.: loral.926
Posted: Mon Sep 23 00:13:01 1985
Date-Received: Sat, 28-Sep-85 05:10:48 EDT
References: <796@kuling.UUCP> <1713@orca.UUCP> <1599@peora.UUCP> <335@ihlpl.UUCP> <2384@uvacs.UUCP> <412@ucsfcca.UUCP>
Reply-To: jvz@loral.UUCP (John Van Zandt)
Organization: Loral Instrumentation, San Diego
Lines: 14

Tagged architectures are nice from a software point of view, but they are
usually poor performers.  One article pointed out that because memory and
silicon are cheap, tagged architectures are now viable.  The performance
of a tagged memory architecture (as with all architectures), is hinged on
the number of memory accesses that must be performed (among other things).
And with a tagged memory system, you must read a memory word before
doing a write (to see if the tag allows writing).  This causes alot of
extra memory accesses and thus detracts from the performance achievable.

John Van Zandt
Loral Instrumentation

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