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Path: utzoo!watmath!clyde!burl!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!mcvax!boring!jack
From: jack@boring.UUCP
Newsgroups: net.micro.68k,net.arch
Subject: Re: Multiple 68020's on VME ?
Message-ID: <6637@boring.UUCP>
Date: Fri, 4-Oct-85 10:49:57 EDT
Article-I.D.: boring.6637
Posted: Fri Oct  4 10:49:57 1985
Date-Received: Sun, 6-Oct-85 04:28:06 EDT
References: <442@rna.UUCP> <1192@vax1.fluke.UUCP>
Reply-To: jack@boring.UUCP (Jack Jansen)
Organization: AMOEBA project, CWI, Amsterdam
Lines: 29
Xref: watmath net.micro.68k:1199 net.arch:1859
Apparently-To: rnews@mcvax.LOCAL


I think that putting multiple CPU's on a VME bus isn't going to
do you a lot of good, unless you either have a lot of local
memory, or a very large cache.

Also, the bus master arbitration of the VME bus is very poor, I think.
Although it is a nice and quite general scheme, performance looks
awful.
It's OK for a DMA device wanting to do a block transfer, but if you
are in a system with 4-8 CPU's and you're all trying to execute
off the bus, you'll probably spend most of your time arbitrating.

At the HTS"A", we're working on a project to put multiple 32016 (with
a lot of cache) on the same VME bus.
What we did is abuse on of the BREQ/BG pairs for bus arbitration:
If you want to do a bus request, you wait 'till you get the BG bit.
Then, you do your request, and pass the BG on to your neighbour/.
If you don't want to do anything, you pass the bit on immedeately.
The CPU that's having the BG at the moment pulls down BREQ, so as soon
as BG 'falls out' of the cardcage, you notice it and generate a new
BG at the beginning of the bus.

This gives a very efficient and fair scheme if you have a reasonable
number of bus masters, who are expected to do large numbers of small
transfers, in stead of small numbers of large ones.
Also, you can still use ordinary VME boards.
-- 
	Jack Jansen, jack@mcvax.UUCP
	The shell is my oyster.


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