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Path: utzoo!watmath!clyde!cbosgd!apr!thompson
From: thompson@apr.UUCP (The Software Warrior)
Newsgroups: net.micro,net.micro.atari
Subject: ST Hard Disk Port (FASI) ?
Message-ID: <123@apr.UUCP>
Date: Sun, 15-Sep-85 15:17:42 EDT
Article-I.D.: apr.123
Posted: Sun Sep 15 15:17:42 1985
Date-Received: Mon, 16-Sep-85 03:14:06 EDT
Reply-To: thompson@apr.UUCP (The Software Warrior)
Organization: Advanced Programming Resources, Columbus OH
Lines: 62
Xref: watmath net.micro:11975 net.micro.atari:1130


Somewhere not to long back I read that the ST had an industry standard
FASI(?) hard disk interface. At the time I passed it off as being a typo
meant to say SASI. However, after staring at the pinout for a while, I
realized that the intended interface was some sort of parallel interface
with DMA capability and that the lines available were actually processor
bus lines. Since they provide only one address line, and only eight data
lines with no UDS or LDS, I assume that their can only be two I/O
registers. The port configuration looks very similiar to what the NCR
5385 SCSI protocol controller chip provides but without enough address
lines to get at the full set of control/status ports. Anyhow what I was
wondering ...

1. Does anyone know if there is such a thing as a FASI interface, and if
   so where can I get information on it? (Any leads at all appreciated.)

2. Does anyone know what is inside a developers hard disk. If there is a
   certain chip (or chips) that is being used to talk to a standard hard
   disk interface (Xebec, or SASI) ? 

3. Do any of the software developers know what the format of the hard
   disk registers are ? (If the format is simple enough this could help
   alot.)

4. Basically any information at all about this hard disk port on the ST
   would be appreciated.

The end result of this all is that I am trying to hang a hard disk on
this monster that I already have. 

Pin out of the ST Hard Disk Port.

1 - Data 0	2 - Data 1      Pins 11,13,15, and 17 Ground
3 - Data 2 	4 - Data 3
5 - Data 4	6 - Data 5
7 - Data 6	8 - Data 7

9 - Chip Select (Probably Decoded Inside the ST to select the interface
    port.)

10 - Interrupt Request (Probably an interrupt to the 68000)

12 - Reset (Probably a reset signal from the 68000)

14 - Acknowledge (Probably a DMA data acknowledge signal)

19 - Data Request (Probably a DMA request to the DMA controller in the ST)

16 - A1 (Probably an address line that selects between to registers on
     the interface port chip(s).)

18 - Read/Write (Probably processor and DMA generated read/write signals)


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