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From: crandell@ut-sally.UUCP (Jim Crandell)
Newsgroups: net.micro
Subject: Re: NEC V20 8088 compatible microproces
Message-ID: <2957@ut-sally.UUCP>
Date: Fri, 20-Sep-85 23:28:49 EDT
Article-I.D.: ut-sally.2957
Posted: Fri Sep 20 23:28:49 1985
Date-Received: Tue, 24-Sep-85 03:11:04 EDT
References: <207@ittral.UUCP> <53400071@trsvax>
Reply-To: crandell@sally.UUCP (Jim Crandell)
Organization: U. Texas CS Dept., Austin, Texas
Lines: 35

>Their Z80 is called the HD64180.  Apart from adding on-chip MMU,
> ... Hitachi shaved the t-states on many of the old-opcodes.
>Examples:
>	JR	cc,address	on the Z80 was 12 t-states for the
>	jump and 7-t states for the fall-through.
>	On the 64180, it is 8-t for the jump and 6-t for the fall-through.
> ...
>Even the NOP executes in fewer t-states.

Really?  Not a very good idea.  The Z-80 nop is 4 states -- standard
opcode fetch.  Considering the tightness of the read and refresh
cycles in an opcode fetch, a 3-clock nop would absolutely necessitate
eliminating the refresh cycle.  Now, suppose you ran the following code:

  1000h:  NOP           ; 3 clocks
  1001h:  NOP           ; 3 clocks
  1002h:  NOP           ; 3 clocks
    .
    .
    .
  107Ch:  NOP           ; 3 clocks
  107D:   JR   1000h    ; 8 clocks

The loop iteration time at 4 MHz is 95.75 uS, giving a refresh interval
for row 7F of over 12 mS, which is out of spec for every dynamic RAM I've
ever heard of.  Furthermore, if the system RAM capacity is over 64K bytes
(256K if you use 256-K RAMS), and if you decode addresses onto RAS to
save power (as most of us do), then that refresh interval applies to
ALL rows in the devices which don't contain the code.  An artificial
example, you say?  Perhaps so.  But the (often sad) truth is, if there's
a way to do it, sooner or later someone will.
-- 

    Jim Crandell, C. S. Dept., The University of Texas at Austin
               {ihnp4,seismo,ctvax}!ut-sally!crandell


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