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Path: utzoo!linus!philabs!cmcl2!seismo!brl-tgr!tgr!Andreas.Nowatzyk@K.CS.CMU.EDU
From: Andreas.Nowatzyk@K.CS.CMU.EDU
Newsgroups: net.micro
Subject: Re: NEC V20 ---> 8088 (actually CMOS)
Message-ID: <1635@brl-tgr.ARPA>
Date: Sat, 21-Sep-85 17:30:29 EDT
Article-I.D.: brl-tgr.1635
Posted: Sat Sep 21 17:30:29 1985
Date-Received: Wed, 25-Sep-85 07:39:24 EDT
Sender: news@brl-tgr.ARPA
Lines: 29

Sorry to say that, but I think you should do some research on
the physics involwed here.

a) Trilogy failed badly when they attempted Wafer Scale Integration
   (WSI). They were putting a mere 60K gates on a wafer (in ECL
   bipolar) and it dissapates 1000W (that's right one Kilowatt!).
   Their gates wre only marginally faster than current CMOS gates
   (0.7 ns is not uncommon). In addition, CMOS has much nicer
   driving properties when it comes to long wires on the chip,
   has a better noise margin etc. As a data point: ETA uses
   20K gate CMOS arrays, 2 of them form a ALU that outperforms
   the one used in Cyber's 205 supercomputer.

b) Companies are not pushing CMOS because it is fashionable, but
   because it is the only promissing way to achive high logic
   desities *and* high speeds. This is obvious if you look at the
   scaling properties of various tecnology.

BTW: The GF10 outperforms a Cray any time. You shouldn't not
fool yourself with memories of RCA's CA4000 series: that is history.

One last point: Static sensitivity - guess which technolgy is more
prone to fail due to static electricity? Properly protected CMOS
or high desnsity ECL? The answer is not obvious. Remember that the
VAX 8600 had servere problems here (a bipolar ECL machine). The
assembly line is now a strict anti-static environement and every
cabinet comes with built in grounding clips for the field service!

   Cheers  --  Andreas


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