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From: jxw@fas.ri.cmu.edu.ARPA (John Willis)
Newsgroups: net.micro.68k,net.arch
Subject: Re: Multiple 68020's on VME ?
Message-ID: <211@fas.ri.cmu.edu.ARPA>
Date: Sat, 5-Oct-85 13:05:02 EDT
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Posted: Sat Oct  5 13:05:02 1985
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	The reference in Computer Design, August 1 to VMEbus problems
is (loosely) based on problems we experienced several years ago using
Motorola's VM02 cards on a Versabus.  We bought the first and second
cards off the production line for use in prototyping a very early
version of our RapidBus multiprocessors.

	Despite these cards being recommended for use in a multiple
processor configuration, I do not believe that Motorola Microsystems
actually tried to use two in the same backplane for many months after
their release.  The designers had ignored the asynchronous relationship
between local and Versabus requests to the dual port arbiter, resulting
in frequent maloperation (4 to 20 minutes under heavy load).

	It required nearly two years, and several very pointed questions
to get Motorola to produce an ECO.  As far as I know, later versions of
the card increased the arbiter resolution time up to fifty nanoseconds,
dramatically improving reliability.  We have since switched to processor
cards from IBM Instruments (CS-9000) and BioResearch for later and much
larger prototypes.

	In talking with Ken Marrin for the article, we tried to point
out the importance of recognizing and intelligently handling each of the
many asynchronous interfaces designed into both VMEbus and Versabus, with
Motorola as one example.  The VM02 is only one of several cards we have
run into with problems correctly handling the asynchronous interface is
MSI.

	It is disappointing that Motorola has not coupled their support
for asynchronous bus design with responsible literature helping designers
to handle asynchronous interface designs correctly.  I believe that many
of their claimed performance figures for VMEbus ignore synchronizer
resolution delays, resulting in either unreliable or slower systems.

	VMEBus multiprocessors can be built reliabably, but the bus
specifications don't tell you everything you need to know.  For further
information, I urge you to read some of the good papers coming out of
the Washington University Asynchronous Systems Group (T. Chaney et al),
or a very practical article by Stoll at Intel in VLSI Design several
years ago.

					-John