Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site lll-crg.ARpA Path: utzoo!watmath!clyde!burl!ulysses!ucbvax!ucdavis!lll-crg!brooks From: brooks@lll-crg.ARpA (Eugene D. Brooks III) Newsgroups: net.arch Subject: Re: Cray-2 impressions Message-ID: <919@lll-crg.ARpA> Date: Wed, 16-Oct-85 00:07:49 EDT Article-I.D.: lll-crg.919 Posted: Wed Oct 16 00:07:49 1985 Date-Received: Thu, 17-Oct-85 02:06:06 EDT References: <1189@ames.UUCP> <224@well.UUCP> Reply-To: brooks@lll-crg.UUCP (Eugene D. Brooks III) Distribution: net Organization: Lawrence Livermore Labs, CRG Group Lines: 27 >Gene: > Is it true that the CRAY-2 cpu is really a CRAY-1 (not an X-MP) >cpu, meaning that it has only one path to memory and doesnt do >chaining? Yes, it true. >So the only major speedup between the X-mp and -2 >cpu's is the faster clock cycle of the 2, 4.1 ns. yes >Also, I understand that the 256K 64-bit memory is slower than the >memory on the x-mp, but there is a fast 16K memory cache per processor. Yes, the latency of the main memory is a real problem. >So it really looks like a CDC 7600!! I'm sure you would prefer the Cray 2. The user does not see the 16k local memory, the compiler does. >I'd like to see some comparison timings between the x-mp and the 2. When the xmp is benchmarked against the 2 the xmp usually wins unless one can manage to effectively buffer vectors through the 16k cache and make a lot of uses of the vector data. If the cache can't be effectively used and the 3 port architecture is useable on the the loop the xmp wins. PS I haven't heard of a single person who has stood in the middle of the Cray 2 and was not impressed.