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From: freed@aum.UUCP (Erik Freed)
Newsgroups: net.arch,net.micro.68k
Subject: Asynchronous State machines
Message-ID: <389@aum.UUCP>
Date: Mon, 21-Oct-85 18:04:00 EDT
Article-I.D.: aum.389
Posted: Mon Oct 21 18:04:00 1985
Date-Received: Wed, 23-Oct-85 06:15:36 EDT
Distribution: net
Organization: The Aurora Systems Bunch
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Xref: watmath net.arch:1934 net.micro.68k:1255

I have received some mail requesting further info on Asyncronous state
machines. I wish that there were some great book on it that I could
give a pointer to, but I don't know of one. There are some papers such as

	DIRECT IMPLEMENTATION OF ASYNCHRONOUS CONTROL UNITS
	      Lee A. Hollaar Jan 12 1982
	      University of Utah
	      IEEE transactions on Computing 1982

I am not sure how you would get a reprint though.

       The basic topic is covered  (I think) by most textbooks on logic.
It is simply the use of Asynchronous logic to make a finite state machine.
The hard part is solving the problem of Hazards or race conditions. These
are not a problem in syncronous designs. One way of getting around this is
to keep your state transitions dependant on only one input signal(at a time).
This can blow up the number of states and make the design awkward if not 
impossible. This is I'm sure discussed in many texts. (But not in Popular
technical mags which must sell complicated chips to uncomplicated engineers)
	Lots of the designs I see are done in slow sync ways and they
could be done in faster and smaller async circuitry. My point is that most
engineers would rather plug in a sequencer than a delay line and in alot of 
the cases this is a big lose. Once you get used to them they are a blast
to use. 
	     Sorry this is not more help, I learned about these through
word of mouth from someone who was a wizard with them.	    

-- 
-------------------------------------------------------------------------------
                           Erik James Freed
			   Aurora Systems
			   San Francisco, CA
			   {dual,ptsfa}!aum!freed