Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: Notesfiles; site hpfcls.UUCP
Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxt!houxm!vax135!cornell!uw-beaver!tektronix!hplabs!hpfcdc!hpfcls!hpfcla!baker
From: baker@hpfcla.UUCP
Newsgroups: net.arch
Subject: Re: Re: systolic processor?
Message-ID: <119900003@hpfcls.UUCP>
Date: Mon, 21-Oct-85 14:01:00 EDT
Article-I.D.: hpfcls.119900003
Posted: Mon Oct 21 14:01:00 1985
Date-Received: Fri, 25-Oct-85 04:26:27 EDT
References: <815@nmtvax.UUCP>
Organization: 21 Oct 85 12:01:00 MDT
Lines: 37

>     I had an idea about creating a systolic machine, but it might not seem to
> follow any orthodox rules.
> 
> The way I thought of doing it is as follows:
> 
> 1) For each cell, let the cell have a 32 bit mpu with a large amount of local
> memory (1M dynamic) and just enough ROM on board to recognize a PROLOG kernal.
> 
> 2) The interconnection medium would be a one dimensional microwave waveguide
> 
> 3) Each cell would have 2 adjustable listening center frequencies and 1
> adjustable transmitting center frequency.
> 
> 4) Cells would communicate with each other under a distributed contention
> protocol. 
> 
> Does this sound like it makes any sense?

	By definition what you propose is not a systolic machine. A systolic
	machine is:
		
		- Few types of simple cells (Simple logic units & a few words of
		  memory)
		- Data and control flows are simple and regular
		- Memory I/O only on the boundary cells
		- Systolic system: data flows from memory in a rhythmic
		  fashion, passing through many PE's before returning to
		  memory, much like blood flows through the heart.

	References (and good reading):
		"Why Systolic Architectures?", H.T. Kung, Jan. 1982, Computer
		"Design of the PSC: A Programmable Systolic Chip", 
			Fisher,Kung,et.al., Proc. of the Third Caltech Conf.
			on VLSI (also in Sigarch 83 somewhere).

Jim Baker 
hplabs!hpfcla!baker		Hewlett-Packard