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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.arch,net.micro.68k
Subject: Re: Asynchronous State machines
Message-ID: <6077@utzoo.UUCP>
Date: Thu, 24-Oct-85 14:19:04 EDT
Article-I.D.: utzoo.6077
Posted: Thu Oct 24 14:19:04 1985
Date-Received: Thu, 24-Oct-85 14:19:04 EDT
References: <389@aum.UUCP>
Organization: U of Toronto Zoology
Lines: 16

> 	Lots of the designs I see are done in slow sync ways and they
> could be done in faster and smaller async circuitry. My point is that most
> engineers would rather plug in a sequencer than a delay line and in alot of 
> the cases this is a big lose. Once you get used to them they are a blast
> to use. 

One possible reason for the preference for sequencers is that sequencer
timing tolerances can be made quite tight, where delay lines usually have
fairly sloppy specs.  I know this is why I gave up on delay lines for
timing dynamic RAMs -- if you believe in worst-case design, the delay
lines' loose tolerances slow things down seriously.  I admit to not being
an expert in this area, so perhaps there is something I missed, but all
the delay-line specs I saw had an awful lot of +- in them.
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry