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From: clif@intelca.UUCP (Clif Purkiser)
Newsgroups: net.arch
Subject: Re: Re: 386 info
Message-ID: <141@intelca.UUCP>
Date: Mon, 18-Nov-85 13:19:59 EST
Article-I.D.: intelca.141
Posted: Mon Nov 18 13:19:59 1985
Date-Received: Wed, 20-Nov-85 08:26:42 EST
References: <965@mcnc.mcnc.UUCP> <2359@ukma.UUCP>
Distribution: net
Organization: Intel, Santa Clara, Ca.
Lines: 50

> In article <965@mcnc.mcnc.UUCP> jnw@mcnc.UUCP (John White) writes:
> >The registers ax,bx,cx,dx,si,di,sp,bp have been expanded to 32 bits
> >(called eax,ebx ...). Each of these registers has its own set of
> >capabilities (as with the 86). (This means that for a given amount of
> >effort writing an optimizing compiler, code for a clean arcitecture
> >like the 68020 will be better optimized than for the 386.)
> 
> If I understand the literature correctly, each task has a default of
> either 16- or 32-bit operands and addresses.  The former would allow
> for emulating the 286, for example.  The default can be overridden by
> a special prefix, which affects only the next instruction.  Anyway,
> if the default is set for 32-bit operands and addresses, all of a sud-
> den there are also quite a few more addressing options, so that the
> registers are almost truly general purpose.  For example, it is possi-
> ble to multiply any two registers.  (Actually, this particular capabi-
> lity is available even if it is set up for the 16-bit default.)  It is
> also possible to use just about any register as an index register.  (I
> think SP is the only register that can't be used this way - it remains
> almost exclusively as a stack pointer.)  So it should be a lot easier
> to write an optimizing compiler - the only thing is that to use use
> these additional addressing options usually lengthens the instruction
> by an extra byte.
> --
> Samuel A. Figueroa, Dept. of CS, Univ. of KY, Lexington, KY  40506-0027
> ARPA: ukma!sambo<@ANL-MCS>, or sambo%ukma.uucp@anl-mcs.arpa,
>       or even anlams!ukma!sambo@ucbvax.arpa
> UUCP: {ucbvax,unmvax,boulder,oddjob}!anlams!ukma!sambo,
>       or cbosgd!ukma!sambo

I wondered if we would ever see the end of the 
"386 Description:   Commercial hype or Valuable Information" debate 
It looks like the fire has finally stopped (yea).

A very minor correction to Samuel's posting.  Each segment has a default 
operand size not each task.  Therefore a task could have both 32-bit segments 
and existing 16-bit 286 segments.  This would be especially useful if you had 
call existing 286 libraries routines from new 386 applications and didn't have
the source code for the 286 libraries to recompile them.

Intel 386 compilers and linkers support the calling conventions necessary to 
allow the linking of both types of segments together.


-- 
Clif Purkiser, Intel, Santa Clara, Ca.
HIGH PERFORMANCE MICROPROCESSORS
{pur-ee,hplabs,amd,scgvaxd,dual,idi,omsvax}!intelca!clif
	
{standard disclaimer about how these views are mine and may not reflect
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