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From: freed@aum.UUCP (Erik Freed)
Newsgroups: net.arch,net.micro.68k
Subject: Re: Asynchronous State machines
Message-ID: <406@aum.UUCP>
Date: Thu, 21-Nov-85 11:37:42 EST
Article-I.D.: aum.406
Posted: Thu Nov 21 11:37:42 1985
Date-Received: Sun, 24-Nov-85 07:24:07 EST
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Organization: The Aurora Systems Bunch
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> > ...Go lower and you are introducing possible flakiness.
> > especially considering that Fairchild's data just might be self-serving...
> 
> The data that my calculations are based on is experimental measurements
> of metastability, not Fairchild spec sheets.

The settling time of various families usually comes from a manufacturer. I 
just meant that I usually don't rely on a manufacturer to be on the pessimistic
side of things as far as their product is concerned.

> 
> I would also note that a one-in-40-years failure criterion -- which got
> mentioned earlier in this discussion -- is almost certainly far too severe
> to be justified.  Most VLSI *chips* have shorter Mean Time Between Soft
> Errors, especially the complex chips that have been pushed hard for speed.
> (I'm talking about logic, not just memory, by the way.)
> -- 

Once again show us your math. It is more rewarding to actually see what *you*
consider to be your data rate and acceptable MTBF. Bear in mind that these
figures are statistical and the failure *could* happen on the first cycle.
Also the data rates mentioned seem very low for a high throughput vme cycle.
After all, we are talking about *speed*.
-- 
-------------------------------------------------------------------------------
                           Erik James Freed
			   Aurora Systems
			   San Francisco, CA
			   {dual,ptsfa}!aum!freed