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From: stubbs@ncr-sd.UUCP (Jan Stubbs)
Newsgroups: net.arch
Subject: Re: 11/08/85 Dhrystone Benchmark Results
Message-ID: <340@ncr-sd.UUCP>
Date: Fri, 22-Nov-85 17:20:52 EST
Article-I.D.: ncr-sd.340
Posted: Fri Nov 22 17:20:52 1985
Date-Received: Mon, 25-Nov-85 06:48:27 EST
References: <1129@hou2h.UUCP> <643@cornell.UUCP>
Reply-To: stubbs@ncr-sd.UUCP (0000-Jan Stubbs)
Distribution: net.arch
Organization: NCR Corporation, San Diego
Lines: 8
Keywords: dhrystone, cache
Summary: 68020 cache doesn't help much

In article <643@cornell.UUCP> jqj@cornell.UUCP (J Q Johnson) writes:
>How much does a typical cache architecture (say a 4K 2-way associative
>cache, or the onboard cache on a 68020) effect Dhrystone performance?
>
I have found the 256 byte instruction cache on the 68020 to have small impact on dhrystone performance ( <10% ) and in any other larger benchmark program. This is easy to measure as you can turn off the cache. Much more important are 
off chip data and instruction caches if large enough.

Jan Stubbs sdcsvax!ncr-sd!stubbs  619 485-3052