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Path: utzoo!watmath!clyde!burl!ulysses!allegra!geno
From: geno@allegra.UUCP (E.Rice)
Newsgroups: net.arch
Subject: Integer Multiplier Question
Message-ID: <5456@allegra.UUCP>
Date: Wed, 27-Nov-85 09:24:47 EST
Article-I.D.: allegra.5456
Posted: Wed Nov 27 09:24:47 1985
Date-Received: Thu, 28-Nov-85 04:31:19 EST
Distribution: net.arch
Organization: AT&T Bell Laboratories, Murray Hill
Lines: 17

I have a question about hardware integer parallel multipliers.
In many languages, the result of a integer multiply has the same length
as the operands.  Therefore it makes sense when building a parallel
multiplier to only generate the low order
half of the product.  A 32x32 multiplier
which only generates a 32 bit product has about half the hardware of
a multiplier generating a full 64 bit product.  Note that the low order
bit pattern of the product is identical whether the numbers are treated as
2's complement or unsigned.

My questions concerns overflow indication.  I wish to know when the product
is too big to fit in the low order half.  Note that overflow is different
in the 2's complement and unsigned cases.  Is there a simple way to
generate overflow indication for both cases?  By simple I mean much cheaper
than generating all the product bits and then testing them.

Thanks in advance for all advice and references.