Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gitpyr.UUCP
Path: utzoo!watmath!clyde!cbosgd!gatech!gitpyr!don
From: don@gitpyr.UUCP (Don Deal)
Newsgroups: net.micro.6809
Subject: Re: Don't use C "register"
Message-ID: <1130@gitpyr.UUCP>
Date: Mon, 2-Dec-85 20:48:15 EST
Article-I.D.: gitpyr.1130
Posted: Mon Dec  2 20:48:15 1985
Date-Received: Thu, 5-Dec-85 04:25:06 EST
References: <593@ihwpt.UUCP>
Reply-To: don@gitpyr.UUCP (Don Deal)
Distribution: net
Organization: Georgia Institute of Technology
Lines: 19

In article <593@ihwpt.UUCP> knudsen@ihwpt.UUCP (mike knudsen) writes:
> ...  Reason: the U Reg is simply substituted for a
>RAM location, so the LD's and STD's become TFR's.
>TFR is the slowest instruction in the 6809 set.  It is quicker
>to move to/from RAM (in almost any addressing mode)
>than to TFR between two regs.

  How do you figure?  The 'tfr' instruction takes 6 machine cycles, and
a load or store using direct addressing averages 5 cycles.  Using even
the simplest addressing mode, direct, is going to cost you on the average
of 4 cycles more than 'tfr', and the other addressing modes (inherent
excluded) are even more expensive.

  The 'cwai', 'swi2', and 'swi3' instructions are tied for being the
slowest on the 6809; they all consume 20 cycles.
-- 
D.L. Deal, Office of Computing Services, Georgia Tech, Atlanta GA, 30332-0275
Phone: (404) 894-6160 (office) 894-4669 (messages) / BITNET: cc100dd@gitvm1
uucp: ...!{akgua,allegra,amd,hplabs,ihnp4,masscomp,ut-ngp}!gatech!gitpyr!don