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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.arch,net.micro.68k
Subject: Re: Asynchronous State machines
Message-ID: <6148@utzoo.UUCP>
Date: Mon, 18-Nov-85 17:39:40 EST
Article-I.D.: utzoo.6148
Posted: Mon Nov 18 17:39:40 1985
Date-Received: Mon, 18-Nov-85 17:39:40 EST
References: <389@aum.UUCP> <6077@utzoo.UUCP>, <395@aum.UUCP>
Organization: U of Toronto Zoology
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> ...Go lower and you are introducing possible flakiness.
> especially considering that Fairchild's data just might be self-serving...

The data that my calculations are based on is experimental measurements
of metastability, not Fairchild spec sheets.

I would also note that a one-in-40-years failure criterion -- which got
mentioned earlier in this discussion -- is almost certainly far too severe
to be justified.  Most VLSI *chips* have shorter Mean Time Between Soft
Errors, especially the complex chips that have been pushed hard for speed.
(I'm talking about logic, not just memory, by the way.)
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry