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From: rose@uw-beaver (Scott Rose)
Newsgroups: net.arch
Subject: Help Requested on 80386 TLB Details
Message-ID: <1730@uw-beaver>
Date: Thu, 5-Dec-85 17:11:06 EST
Article-I.D.: uw-beave.1730
Posted: Thu Dec  5 17:11:06 1985
Date-Received: Mon, 9-Dec-85 03:06:08 EST
Distribution: net
Organization: U of Washington Computer Science
Lines: 26

I have some questions about how virtual memory is implemented in the 80386;
the little "Introduction to the 80386" blurb that the local rep. mailed me
does not have much detail, and he doesn't seem to have the time required to
explain it to me on the phone.  But netters have all the time in the world,
and I am hoping that one of you will throw together a quick response for me.
Please flame directly to me and I promise not to summarize to the net.
Here is what I wanted to ask my overworked Intel rep.:

% How is the TLB organized?  Is it fully-associative, or direct mapped?

% Doesn't the TLB need to be flushed on a task switch?  How is this flushing
% specified?  Are there any instructions for overtly managing the TLB?

% On a page fault, how is the TLB entry, if any, updated for the replaced
% page?  The present bit must be cleared, and the dirty bit must be read.

% When the OS clears the accessed bits for an address space, does it
% update the TLB entries?

% Can one fault on a page table?  If not, how are these locked into memory?
% How can the processor be sure that a page table directory is present?

% What if IBM had...

	-Scott Rose
	 rose@uw-beaver