Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!henry From: henry@utzoo.UUCP (Henry Spencer) Newsgroups: net.arch,net.micro.68k Subject: Re: Asynchronous State machines Message-ID: <6212@utzoo.UUCP> Date: Mon, 9-Dec-85 19:31:23 EST Article-I.D.: utzoo.6212 Posted: Mon Dec 9 19:31:23 1985 Date-Received: Mon, 9-Dec-85 19:31:23 EST References: <389@aum.UUCP> <6077@utzoo.UUCP> <395@aum.UUCP> <6111@utzoo.UUCP> <6144@utzoo.UUCP> <404@aum.UUCP> <406@aum.UUCP> Organization: U of Toronto Zoology Lines: 57 > I have this feeling that it is probably time for us to see your math... Better late than never. Reference is T.J. Chaney, "Measured Flip-Flop Responses to Marginal Triggering", IEEE Transactions on Computers, Dec 1983. Chaney was first author of the "Beware The Synchronizer" paper that started this whole mess back in 1972, by the way. MTBSU(t) = exp(t/TAU) / (T0 * clockrate * eventrate) where t > h MTBSU(t) is mean time between cases when the synchronizer has not settled by time t after clocking. TAU, T0, and h are experimentally-derived flip- flop parameters. Chaney gives several numbers for S74, all with a worst-case TAU around 1 ns. He also gives F74 as TAU=0.4ns, T0=0.2ms, h=6ns. (Note that these are his measured numbers, not manufacturer-derived optimism.) The TAU numbers are quite accurate, +- 50 ps. h is +- 3 ns, but it's only a constraint anyway. T0 is fairly inaccurate, */ 10 (that is +1000%/-90%). Note that TAU is the parameter that really matters, since it's inside an exponential. Chaney's data does show considerable variation in TAU among parts and between manufacturers, so let's try a range of TAU values. The following is for the F74 with Chaney's T0 assumed to contain a worst-case error (+1000%). Clock is 27.6 MHz (period 36.2 ns), event rate is one in 16 clocks average. t is one clock tick (36.2 ns) after clocking. TAU MTBSU 0.4 1.8e27 0.45 9e23 0.5 2.9e20 0.6 1.7e15 0.7 3e11 0.8 4.7e8 0.9 3e6 1.0 5.5e4 (1e5 ~ day, 1e8 ~ 3 years, 1e10 ~ 3 centuries.) Even if we assume Chaney's F74 TAU is wrong by a factor of two, MTBSU is still over a decade. Note that this is with a severe worst-case error in his T0; remove that and MTBSU is over a century. Since I have a low opinion of the mean-time-between-soft-errors of things like 32-bit MOS processors, this seems entirely adequate to me. Note the way the numbers go: because of the exponential, MTBSU is *fiercely* dependent on TAU. That factor of two from 0.4 to 0.8 cuts MTBSU by over 18 orders of magnitude! I repeat a previous comment: for synchronizers, FTTL is not just better than STTL, it is lots better. The one annoyance is that it would be nice to have better data. Chaney's sample of FTTL was pretty small, and old (date code 1979). Chaney notes that the numbers tend to get better with time as the parts are souped up. Anybody know of more recent test runs for FTTL? I don't normally follow IEEE Trans Comp, I just happened to encounter a reference to this paper. -- Henry Spencer @ U of Toronto Zoology {allegra,ihnp4,linus,decvax}!utzoo!henry