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From: brooks@lll-crg.ARpA (Eugene D. Brooks III)
Newsgroups: net.arch
Subject: Re: Virtual mem
Message-ID: <1128@lll-crg.ARpA>
Date: Tue, 10-Dec-85 03:13:09 EST
Article-I.D.: lll-crg.1128
Posted: Tue Dec 10 03:13:09 1985
Date-Received: Wed, 11-Dec-85 04:20:21 EST
References: <34548@lanl.ARPA> <2511@umcp-cs.UUCP>
Reply-To: brooks@lll-crg.UUCP (Eugene D. Brooks III)
Distribution: net
Organization: Lawrence Livermore Labs, CRG Group
Lines: 20

In article <2511@umcp-cs.UUCP> mangoe@umcp-cs.UUCP (Charley Wingate) writes:
>This is fine in systems where there isn't malicious code.  In commercial
>applications, one must assume there is deliberately destructive code.
You can have memory protection without paging.  It is done with base
and limit registers for memory addresses.  This is a different issue than
whether you want demand paging.

>retrieval systems.  These programs tend to have data swapping built into
>them (since they tend to allow for unlimited expansion through the use of
>files), so why should there be an objection to using paging?
Using paging is certainly not objectionable if it does not slow the computer
down.  On Vax class machines where the hardware is slow in the first place
is it easy to create page mapping hardware that can keep up with the cpu
memory requests.

In machines with significant scalar speed, such as the Cray series,
the scalar speed is so fast that you can not implement a memory cache or
paging without sacrificing scalar performance.  As the primary reason why
CRI holds the lion's share of the supercomputer market is scalar performance
it don't think they will be putting in paging very soon.