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From: clif@intelca.UUCP (Clif Purkiser)
Newsgroups: net.arch
Subject: Re: Help Requested on 80386 TLB Details
Message-ID: <150@intelca.UUCP>
Date: Wed, 11-Dec-85 14:10:53 EST
Article-I.D.: intelca.150
Posted: Wed Dec 11 14:10:53 1985
Date-Received: Sat, 14-Dec-85 00:42:30 EST
References: <1730@uw-beaver>
Distribution: net
Organization: Intel, Santa Clara, Ca.
Lines: 52

> I have some questions about how virtual memory is implemented in the 80386;
> the little "Introduction to the 80386" blurb that the local rep. mailed me
> does not have much detail, and he doesn't seem to have the time required to
> explain it to me on the phone.  But netters have all the time in the world,
> and I am hoping that one of you will throw together a quick response for me.
> Please flame directly to me and I promise not to summarize to the net.
> Here is what I wanted to ask my overworked Intel rep.:
> 
> % How is the TLB organized?  Is it fully-associative, or direct mapped?
> 
32 Entries.   4-way set associative.

> % Doesn't the TLB need to be flushed on a task switch?  How is this flushing
> % specified?  Are there any instructions for overtly managing the TLB?
> 
No it doesn't .  Either a MOV CR3, Reg instruction which loads the page
directory root register or a Task Switch which causes the value of CR3 to
be different.  No explicit instructions exist for managing the TLB other than
instructions used by a test engineer.


> % On a page fault, how is the TLB entry, if any, updated for the replaced
> % page?  The present bit must be cleared, and the dirty bit must be read.
> 
The new TLB entry replaces an old TLB entry using an Intel proprietary 
algorithim.  The present, R/W, U/S bit in the TLB are set.  

> % When the OS clears the accessed bits for an address space, does it
> % update the TLB entries?
> 
Yes it should flush the TLB to ensure the TLB entries match the page table
entries.
> % Can one fault on a page table?  If not, how are these locked into memory?
> % How can the processor be sure that a page table directory is present?
> 
Yes one can fault on a page table.  The page table directory however must
be always be present.

> % What if IBM had...
Used a 6502.  My former company VisiCorp would still be in business because
Lotus 1-2-3 wouldn't fit in 64K .
> 
> 	-Scott Rose
> 	 rose@uw-beaver

-- 
Clif Purkiser, Intel, Santa Clara, Ca.
HIGH PERFORMANCE MICROPROCESSORS
{pur-ee,hplabs,amd,scgvaxd,dual,idi,omsvax}!intelca!clif
	
{standard disclaimer about how these views are mine and may not reflect
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