Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 (Tek) 9/28/84 based on 9/17/84; site tekig4.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxt!houxm!vax135!cornell!uw-beaver!tektronix!tekig5!tekig4!halp From: halp@tekig4.UUCP (Hal Porter) Newsgroups: net.arch Subject: Info on parallel processor and memory interconnection Message-ID: <444@tekig4.UUCP> Date: Fri, 20-Dec-85 17:14:44 EST Article-I.D.: tekig4.444 Posted: Fri Dec 20 17:14:44 1985 Date-Received: Sun, 22-Dec-85 00:29:46 EST Organization: Tektronix, Beaverton OR Lines: 20 schemes ------- I have been searching for information on the following subjects and I am not having much luck finding pertinent info. I would appreciate any references that you in net-land feel might be interesting and/or educational reading. Both academic research and "real" world application information will be greatly appreciated. Please respond by e-mail. 1) Parallel (not distributed) processor interconnection schemes. 2) Parallel processor shared memory interconnection schemes 3) Cache memory methods, techniques, trade-offs, etc. 4) Parallel concurrent programming methods, techniques, etc. 5) Anything dealing with parallel concurrent processing. Thanks in advance, Hal Porter ...tektronix!halp