Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site lll-crg.ARpA
Path: utzoo!watmath!clyde!burl!ulysses!gamma!epsilon!zeta!sabre!petrus!bellcore!decvax!ucbvax!ucdavis!lll-crg!brooks
From: brooks@lll-crg.ARpA (Eugene D. Brooks III)
Newsgroups: net.arch
Subject: Re: caches in vector machines
Message-ID: <1151@lll-crg.ARpA>
Date: Tue, 24-Dec-85 03:16:26 EST
Article-I.D.: lll-crg.1151
Posted: Tue Dec 24 03:16:26 1985
Date-Received: Wed, 25-Dec-85 03:35:47 EST
References: <125@decwrl.DEC.COM>
Reply-To: brooks@lll-crg.UUCP (Eugene D. Brooks III)
Organization: Lawrence Livermore Labs, CRG Group
Lines: 8


As for the Cray series, the clock speed is just too fast to build a cache.
The vector registers are used for explicit caching.

Take note that in the Convex C1 where the clock speed is slow enough to
allow a conventional cache, the vector functional units bybass the cache.
This done to keep vector operations from flushing the scalars out of the
cache.