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From: rchrd@well.UUCP (Richard Friedman)
Newsgroups: net.arch
Subject: Re: caches in vector machines
Message-ID: <391@well.UUCP>
Date: Tue, 24-Dec-85 15:15:44 EST
Article-I.D.: well.391
Posted: Tue Dec 24 15:15:44 1985
Date-Received: Wed, 25-Dec-85 23:32:30 EST
References: <125@decwrl.DEC.COM>
Organization: Whole Earth Lectronic Link, Sausalito, CA
Lines: 34
Summary: Cached vector machines I have known...

In article <125@decwrl.DEC.COM>, jbell@grofe.DEC (Jeff Bell) writes:
> Most people agree that cacheing is a good way to improve the performance
> of scalar machines.  Does anyone have information on the use of caches
> in vector machines?  Has anyone ever built a cached vector machine?
> How much bigger does it have to be to get a reasonable hit rate.
> 
> Jeff Bell
> ARPA:	jbell%tallis.DEC@decwrl.ARPA
> UUCP:	....!decwrl!tallis!jbell
> 

The Alliant FX/8 and the IBM 3090 (370-XA) are chached vector machines.
(Virtual memory).  As a result, both Alliant and IBM are looking at
new algorithms that take the cache in mind.  With these machines it
is possible to be computing thru the cache faster than the cache can
be filled from real memory.  The result is that after some problem size
the performance is degraded.  New algorithms (FFT, LINPACK etc) must
be devised that "strip mine" the problem so as much as possible can
fit into the cache.

    ...Richard Friedman [rchrd]
       Pacific-Sierra Research
       2855 Telegraph #415, Berkeley CA 94705
       (415) 540 5216
     
       USENET:  {lll-crg,ptsfa,hplabs}!well!rchrd
-- 

    ...Richard Friedman [rchrd]
       Pacific-Sierra Research
       2855 Telegraph #415, Berkeley CA 94705
       (415) 540 5216
     
       USENET:  {lll-crg,ptsfa,hplabs}!well!rchrd