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From: kds@intelca.UUCP (Ken Shoemaker)
Newsgroups: net.arch
Subject: Re: TLB entry invalidation
Message-ID: <161@intelca.UUCP>
Date: Thu, 26-Dec-85 14:36:14 EST
Article-I.D.: intelca.161
Posted: Thu Dec 26 14:36:14 1985
Date-Received: Sat, 28-Dec-85 13:03:11 EST
References: <1730@uw-beaver> <2619@sjuvax.UUCP> <867@x.UUCP> <2659@sjuvax.UUCP>
Distribution: net
Organization: Intel, Santa Clara, Ca.
Lines: 19

> 
> Intel does not have a clear TLB instruction *or* pin, and as such, if
> one processor robs another of a page belonging to the running process
> you are in deep dip.  If sbrk needs to allocate and validate a new
> page as existing, there is no problem.  The problem is invalidating an
> old page.  Since the 80386 provides no way to flush the TLB without
> doing a process exec, this isn't possible.  Besides, on a real system
>
Er, as I have said before, to flush the TLB, all one needs do is reload
CR3, which is the page table base pointer.  If you load it with the same
value (which you can get, since it is also readable), then you have
flushed the TLB without changing the address map.
-- 
remember, if you do it yourself, sooner or later you'll need a bigger hammer

Ken Shoemaker, Santa Clara, Ca.
{pur-ee,hplabs,amd,scgvaxd,dual,qantel}!intelca!kds
	
---the above views are personal.