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From: brianu@ada-uts.UUCP
Newsgroups: net.arch
Subject: Re: Re: caches in vector machines and Dh
Message-ID: <7900006@ada-uts.UUCP>
Date: Mon, 30-Dec-85 09:55:00 EST
Article-I.D.: ada-uts.7900006
Posted: Mon Dec 30 09:55:00 1985
Date-Received: Wed, 1-Jan-86 04:44:49 EST
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Nf-From: ada-uts!brianu    Dec 30 09:55:00 1985


>Mike Taylor  ...!{ihnp4,hplabs,amd,sun}!amdahl!mat  writes:
>For what it's worth, Fujitsu VPs do I-fetch from cache.  Operand fetch
>proceeds directly from mainstore via load/store pipe(s).

The Cray machines also do instruction fetches out of a cache.
Instructions are executed from the "instruction buffers". if the required
instruction is in the buffers it is issued from there; otherwise a buffer
load is performed on the least recently loaded buffer.  Although the
buffer is always on a 16 word boundry, the buffer is loaded starting with
the required instruction so that execution may continue as soon as
possible.
The Cray 1S has 4 16-word buffers, the XMP has 4 32-word buffers and the
Cray 2 has 8 16-word buffers.  Each word is 64-bits and is subdivided
into 4 16-bit parcels. An instruction can be either 1 or 2 parcels on
either the 1S or XMP, while it can be up to 5 parcels on the Cray 2.
Unforunately, since the buffer are reloaded in round-robin fashion, it
is not possible to maintain a small kernel in one or two buffers while
using the rest for subroutine calls.  A better algorithm would be least
recently used, but was probably to slow.

Brian Utterback
Intermetrics Inc.
733 Concord Ave. Cambridge MA. 02138. (617) 661-1840
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